Kamis, 27 Desember 2012

Square law modulator using orcad capture

This short video demonstration shows square law modulator operation principle using orcad capture.

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The schematic is below-

square law modulator

Minggu, 16 Desember 2012

D Flip Flop realization and simulation using Xilinx, Isim and Modelsim

The video below shows D Flip Flop realization in verilog HDL and simulation using Xilinx and Modelsim. First D Flip Flop is constructed in Xilinx, then it's stimulus is created also in Xilinx and then simlated using Isim and Modelsim.

Below is the video, code and some screenshots of the D flip flop schematic-

Video-


Schematics-

D Flip Flop
Fig: D Flip Flop
A closer look of D Flip Flop
Fig: A closer look of D Flip Flop
Verilog Codes:

A. D Flip Flop Verilog HDL code:
------------------------------------------------------------------
// D Flip Flop

module dff(
    input D,
    output reg Q,
    output reg Qn,
    input clk,
    input rst
    );
   
     always @(posedge clk or negedge rst)
        begin
            if(rst == 1'b0)
                begin
                    Q <= 0;
                    Qn <= 1;
                end
            else
                begin
                    Q <= D;
                    Qn <= !D;
                end
        end

endmodule
--------------------------------------------------------------------

B. Test Module for D Flip Flop
------------------------------------------------------------------------
// Test Bench for D Flip Flop

`timescale 1ns / 10ps

module dff_test;

    //Time Parameter
    localparam T = 20;  //20ns

    // Inputs
    reg D_t;
    reg clk_t;
    reg rst_t;

    // Outputs
    wire Q_t;
    wire Qn_t;

    // Instantiate the Unit Under Test (UUT)
    dff uut (
        .D(D_t),
        .Q(Q_t),
        .Qn(Qn_t),
        .clk(clk_t),
        .rst(rst_t)
    );
----------------------------------------------------------------

Jumat, 14 Desember 2012

Kamis, 13 Desember 2012

Comsol Multiphysics Tutorial: Setting up boundary

This is a simple quick video on setting up boundary condition and mesh in Comsol Multiphysics. In this exercise a simple rectangular geometry is created and mesh are defined.


Multiplexer Design and Simulation using Xilinx and Modelsim Video Tutorial

The following quick video tutorial shows 4x1 Multiplexer design and simulation using Xilinx and Modelsim. The HDL language used in Verilog. Multiplexers are essential combinational circuit elements that are required and used in larger FPGA design. First 4x1 Mulitplexer verilog code is constructed then the test bench is created in Xilinx ISE and finally simulated in Modelsim 10.1c to verify it's correctness.

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Rabu, 12 Desember 2012

Modelsim logic gate video tutorial

This is a quick video tutorial on how to use Modelsim for logic gate design and verification. An AND gate is constructed with verilog HDL and a testbench is also created to test it's logic. We start by creating a project in Modelsim, then create an AND gate and then the testbench. Finally operation of the gate is checked through simulation.

Watch the video below-



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AND Gate verification using Xilinx and Modelsim

This quick video tutorial shows how to verify AND gate logic using Xilinx and Modelsim. Xilinx v13 and modelsim 10.1c has been used here. First a new project is created in xilinx, verilog code for AND gate is created and then verilog code for test bench is created. The code syntax is checked for correctness and then simulated using Modelsim simulator. The output corresponding to the four logic combination input, that is, 00, 01, 10 and 11 is checked.

watch the following video-



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