Multiplexer Design and Simulation using Xilinx and Modelsim Video Tutorial

The following quick video tutorial shows 4x1 Multiplexer design and simulation using Xilinx and Modelsim. The HDL language used in Verilog. Multiplexers are essential combinational circuit elements that are required and used in larger FPGA design. First 4x1 Mulitplexer verilog code is constructed then the test bench is created in Xilinx ISE and finally simulated in Modelsim 10.1c to verify it's correctness.

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