AND Gate verification using Xilinx and Modelsim

This quick video tutorial shows how to verify AND gate logic using Xilinx and Modelsim. Xilinx v13 and modelsim 10.1c has been used here. First a new project is created in xilinx, verilog code for AND gate is created and then verilog code for test bench is created. The code syntax is checked for correctness and then simulated using Modelsim simulator. The output corresponding to the four logic combination input, that is, 00, 01, 10 and 11 is checked.

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