D Flip Flop realization and simulation using Xilinx, Isim and Modelsim

The video below shows D Flip Flop realization in verilog HDL and simulation using Xilinx and Modelsim. First D Flip Flop is constructed in Xilinx, then it's stimulus is created also in Xilinx and then simlated using Isim and Modelsim.

Below is the video, code and some screenshots of the D flip flop schematic-

Video-

Schematics-

Fig: D Flip Flop

Fig: A closer look of D Flip Flop

Verilog Codes:

A. D Flip Flop Verilog HDL code:
------------------------------------------------------------------
// D Flip Flop

module dff(
    input D,
    output reg Q,
    output reg Qn,
    input clk,
    input rst
    );
   
     always @(posedge clk or negedge rst)
        begin
            if(rst == 1'b0)
                begin
                    Q <= 0;
                    Qn <= 1;
                end
            else
                begin
                    Q <= D;
                    Qn <= !D;
                end
        end

endmodule
--------------------------------------------------------------------

B. Test Module for D Flip Flop
------------------------------------------------------------------------
// Test Bench for D Flip Flop

`timescale 1ns / 10ps

module dff_test;

    //Time Parameter
    localparam T = 20;  //20ns

    // Inputs
    reg D_t;
    reg clk_t;
    reg rst_t;

    // Outputs
    wire Q_t;
    wire Qn_t;

    // Instantiate the Unit Under Test (UUT)
    dff uut (
        .D(D_t),
        .Q(Q_t),
        .Qn(Qn_t),
        .clk(clk_t),
        .rst(rst_t)
    );
----------------------------------------------------------------